Class D amplifiers

This final year project aims to design an audio single-ended filterless Class D amplifier used in earpiece. A 3-level PWM signal is to be produced at the load for this purpose. Due to the fact that both left and right channels of earpiece share the common ground, the single-ended structure is required for the purpose of this study. During the design process, a digital control block is successfully designed to transform the 2-state PWM signal into a 3-state PWM signal. Meanwhile, a digital buffer is designed to achieve a high forward loop gain in order to attenuate the noise. A hysteresis comparator is designed to generate the control signal. The single-ended filterless Class D amplifier is designed with high fidelity. Simulations are carried out in Cadence Spectre with CSM018 process. This design is verified to have achieved high PSRR (>120dB at 1 kHz) and low THD (