The purpose of this project is to simulate the post-breakdown transistor performance in ultrathin gate dielectric. The simulator used was TSUPREM-4 and MEDICI, which is widely used in the semiconductor industry for simulation and analyze semiconductor processing. The simulation was done on a 0.13μm metal-oxide-semiconductor field-effect transistor (MOSFET) which has silicon and silicon oxide defects introduced into the gate dielectric. Various different doping defects and silicon oxide defects are added into the simulation to test for the post-breakdown I-V characteristics of the transistor.Bachelor of Engineerin
In this work, a simulation methodology, whose inputs are Conductive Atomic Force Microscope (CAFM) e...
The further improvement of nanoscale electron devices requires support by numerical simulations with...
The extensive simulations are carried out to study impact of high K dielectric both on the channel a...
In this project, the mechanism of Dielectric Breakdown Induced Epitaxy (DBIE) growth and its effects...
Progressive breakdown has been found to provide an extra post-breakdown reliability margin for devic...
The potential impact of high-κ gate dielectrics on device short-channel performance is studied over ...
Coupled process and device simulation has been applied to investigate the physical processes which d...
The classical planar Metal Oxide Semiconductor Field Effect Transistors (MOSFET) is fabricated by ox...
Scaling down the dimensions of Metal Oxide Semiconductors (MOS) to nano-scale has resulted\ud in deg...
The rapid downscaling of contemporary bulk CMOS devices has worsened the negative bias temperature i...
90 p.The purpose of this project is to study the gate oxide breakdown in ultra-thin pMOSFETs using c...
The initial stage of the project involved the development of a new ultra-fast switching (UFS) method...
An increase in worldwide investments during the past several decades has pro-pelled scienti c breakt...
In this work we present a novel simulation-based methodology for the defect spectroscopy in dielectr...
Die fortschreitende Skalierung und zunehmende Packungsdichte integrierter Schaltkreise führt zu imme...
In this work, a simulation methodology, whose inputs are Conductive Atomic Force Microscope (CAFM) e...
The further improvement of nanoscale electron devices requires support by numerical simulations with...
The extensive simulations are carried out to study impact of high K dielectric both on the channel a...
In this project, the mechanism of Dielectric Breakdown Induced Epitaxy (DBIE) growth and its effects...
Progressive breakdown has been found to provide an extra post-breakdown reliability margin for devic...
The potential impact of high-κ gate dielectrics on device short-channel performance is studied over ...
Coupled process and device simulation has been applied to investigate the physical processes which d...
The classical planar Metal Oxide Semiconductor Field Effect Transistors (MOSFET) is fabricated by ox...
Scaling down the dimensions of Metal Oxide Semiconductors (MOS) to nano-scale has resulted\ud in deg...
The rapid downscaling of contemporary bulk CMOS devices has worsened the negative bias temperature i...
90 p.The purpose of this project is to study the gate oxide breakdown in ultra-thin pMOSFETs using c...
The initial stage of the project involved the development of a new ultra-fast switching (UFS) method...
An increase in worldwide investments during the past several decades has pro-pelled scienti c breakt...
In this work we present a novel simulation-based methodology for the defect spectroscopy in dielectr...
Die fortschreitende Skalierung und zunehmende Packungsdichte integrierter Schaltkreise führt zu imme...
In this work, a simulation methodology, whose inputs are Conductive Atomic Force Microscope (CAFM) e...
The further improvement of nanoscale electron devices requires support by numerical simulations with...
The extensive simulations are carried out to study impact of high K dielectric both on the channel a...