Development of an advanced nano-satellite VELOX-I - Study of high dynamic range CMOS image sensor and pixel design

The Undergraduate Satellite Programme is a real-world engineering project participated by engineering students, school staff, and professors to build and launch Singapore’s first home developed satellites. The Velox-I nano-satellite is scheduled to be launched next and one of its subsystems is the camera payload. The basic building block of a camera system is the pixels located within the image sensor, which converts optical signals into electrical signals. One quality factor to consider is the Dynamic Range of the pixel, which determines the amount of detail the pixel can provide at different illuminated conditions. This thesis presents the study of CMOS image sensors, discussing the operation of photo-conversion and the study of different pixel architectures. The information obtained will be used for the design of a high dynamic range pixel, with a targeted range of 100dB for satellite applications. A pixel with a combined linear-logarithmic (CLL) response was designed, which integrates the linear response exhibited from the 3 Transistor Active Pixel Sensor (3T-APS) and the voltage compression from the Logarithmic Pixel. For a 100dB range of photocurrent from 100fA to 10nA, the 3T-APS reaches saturation at a limited exposure time, while the logarithmic pixel exhibits a narrow non-linear output voltage swing. The CLL pixel does not reach saturation at 10nA, which implies a dynamic range of over 100dB was achieved in the design. Theoretical analysis also shows that the transition from linear to logarithmic is time dependant. The column bias transistor and voltage buffer was also designed as part of a test structure for validating the pixel performance after fabrication. Specifications of the analogue components are suited for 8MHz sampling operation. Simulation results have shown the successful reflection of the 100dB dynamic range at the column bus and the output pad, as well as the potential areas to be improved to limit variation effects due to temperature. The pixels and test structure will be fabricated using the 65nm CMOS process by Global Foundries. The different layout design practices and techniques implemented such as the guard ring, N-well photodiode and interdigitated transistors will be presented.Bachelor of Engineerin