Design of a sub-1V low-dropout (LDO) voltage regulator in FinFET technology

Trends in multi-gigahertz analog and RF circuits designed in deep-submicron technology requires ever-low power supply. This has given boost to a whole new area of low-power, high speed consumer electronics. However, increasing speed of operation needs more current and consequently increased power dissipation on a small area. A well-conditioned power supply is key to the performance of any sub-micron MOSFET analog circuit. However, changing load conditions incur transients that cause the supply to become noisy where there is a need of direct-current (DC) component. To remove these inefficiencies of a power supply there is a growing demand for efficient voltage regulators as the performance of the regulator in the operational bandwidth helps to minimize these fluctuations. In this master thesis, two supply lines have been used to implement a low-dropout linear voltage regulator. Normally, a PMOS pass element is used to realise a regulator circuit however here an NMOS pass element has been used to weigh in its advantages over the PMOS counterpart especially on account of lower area and better dynamic performance. The NMOS regulator is able to maintain a constant output current around 20mA under fast loading and unloading conditions. To lower the current consumption in the overall design, a specific architecture of operational transconductance amplifier (OTA) has been employed which also renders the stabilisation of LDO architecture easy. The dual supply line LDO also helps keeping the LDO drop-out voltage low (150mv) making it a low power consumption device which is key to the performance of any handheld device. The regulator quiescent current at no-load condition is 17.7µA. ii The simulated (schematic) performance is: Vout (LDO output voltage) = 798.95 mV σ (standard deviation) Vout = 0.325% VDD (OTA power supply) = 1.25V VIN (LDO input voltage) = 0.95V Efficiency = 83.95%Master of Science (Integrated Circuit Design