Wire bond technology is a matured and dominant interconnect methodology compared to other chip interconnect methodologies. The parasitic components of the bond wire, especially in high speed operating conditions, have to be modeled accurately before utilizing the bond wire in such designs. Our research group is working on a novel high-efficiency Class-E switched-mode Power Amplifier (PA) IC for digital RF transmitters [5]. The PA employs a novel digitally-controlled matching network that utilizes switched-capacitors and wire bonds to the board. This requires accurate modeling of the required wire bonds for its inductance. Our research group also works on a novel high-rate Analog-to-Digital Converter (ADC) for switched-mode DC-DC converters...
When making an Integrated Chip, there is a process called contacting or bonding. In this process, th...
Thesis: S.M., Massachusetts Institute of Technology, Department of Mechanical Engineering, 2014.This...
Abstract — Noise induced by impedance discontinuities from VLSI pack-aging is one of the leading cha...
In the current semiconductor industry, the technology of semiconductor is more advanced and the size...
Bonding wires are extensively used in integrated circuit (IC) packaging and circuit design in RF app...
A full-wave modeling procedure was developed to simulate the package, bonding wires, and MOS capacit...
International audienceThis article presents a modeling and parametric investigation of PCB (printed ...
Power supply designs are often overlooked as part of a high-frequency electronic system. A wide rang...
Escalating demands for personal wireless communication equipment have spearheaded development of aff...
This electronic version was submitted by the student author. The certified thesis is available in th...
The concept of coupled multiturn bondwire inductors with ferrite epoxy glob cores is investigated bo...
In this contribution, the authors present a systematic approach for optimizing the RF performance of...
The focus of this project is to study the causes of and design considerations for reducing the impac...
Novel analytical models for accurately and efficiently calculating the inductances of bond wires in ...
Many integrated circuits are connected to their packaging pins through bondwires. Due to the low cos...
When making an Integrated Chip, there is a process called contacting or bonding. In this process, th...
Thesis: S.M., Massachusetts Institute of Technology, Department of Mechanical Engineering, 2014.This...
Abstract — Noise induced by impedance discontinuities from VLSI pack-aging is one of the leading cha...
In the current semiconductor industry, the technology of semiconductor is more advanced and the size...
Bonding wires are extensively used in integrated circuit (IC) packaging and circuit design in RF app...
A full-wave modeling procedure was developed to simulate the package, bonding wires, and MOS capacit...
International audienceThis article presents a modeling and parametric investigation of PCB (printed ...
Power supply designs are often overlooked as part of a high-frequency electronic system. A wide rang...
Escalating demands for personal wireless communication equipment have spearheaded development of aff...
This electronic version was submitted by the student author. The certified thesis is available in th...
The concept of coupled multiturn bondwire inductors with ferrite epoxy glob cores is investigated bo...
In this contribution, the authors present a systematic approach for optimizing the RF performance of...
The focus of this project is to study the causes of and design considerations for reducing the impac...
Novel analytical models for accurately and efficiently calculating the inductances of bond wires in ...
Many integrated circuits are connected to their packaging pins through bondwires. Due to the low cos...
When making an Integrated Chip, there is a process called contacting or bonding. In this process, th...
Thesis: S.M., Massachusetts Institute of Technology, Department of Mechanical Engineering, 2014.This...
Abstract — Noise induced by impedance discontinuities from VLSI pack-aging is one of the leading cha...