Simulation of neural networks for neuromorphic chip with crossbar array of RRAM synapses

The proliferation in use of data-intensive statistical models and algorithms have given a push to the brain-inspired computing, commonly known as Neuromorphic computing. With the increased research interest in neuromorphic computing, neuromorphic chip, a dedicated hardware for realizing neural networks (NN), is gaining popularity. However, the challenge is to design an efficient neuromorphic chip in terms of area density, power consumption and scalability, which can incorporate huge number of neurons similar to what is found in the human brain. In this thesis, an automated technique for mapping any feed-forward deep neural network onto the neuromorphic chip is discussed, where mapping refers to the generation of connectivity list based on the interrelation of neurons in adjacent neural network layers and assigning those neurons to specific addresses in neuromorphic core. Furthermore, it acts as a simulation tool for debugging computations performed on the neuromorphic chip during inferencing. Together the configuration becomes Mapping and Debugging (MaD) framework[1]. MaD framework is quite general in usage and can also be used for very popular IBM TrueNorth chip. This paper illustrates the MaD framework in detail, considering some optimizations while mapping. A classification task on MNIST and CIFAR-10 datasets are considered for test case implementation of MaD framework.Master of Science (Green Electronics