We propose 3D mesh-based optical network-on-chip (ONoC) based on a novel low-cost 6×6 optical router, and quantitatively analyze thermal effects on the 3D ONoC. Evaluation results show that with the traditional thermal tuning technique using microheater, the average power efficiency of the 3D ONoC is about 2.7pJ/bit, while chip temperature varies spatially between 55°C and 85°C. In comparison, a new technique using the optimal device setting can improve the average power efficiency to 2.1pJ/bit. It is shown that in this particular case, the effectiveness of the two techniques is comparable. If we apply both techniques at the same time, the average power efficiency can be further improved to 1.3pJ/bit
Network-on-chip (NoC) can improve the performance, power efficiency, and scalability of multiprocess...
Three dimensional Networks-on-Chip (3D NoCs) have attracted a growing interest to solve on-chip comm...
Three dimensional (3D) integration technologies have a smaller footprint area of chip compared to th...
We propose 3D mesh-based optical network-on-chip (ONoC) based on a novel low-cost 66 optical router,...
The performance of multiprocessor systems, such as chip multiprocessors (CMPs), is determined not on...
Optical network on chip is an emerging research topic, which can provide low latency and high bandwi...
The performance of multiprocessor systems, such as chip multiprocessors (CMPs), is determined not on...
Network-on-chip (NoC) can improve the performance, power efficiency, and scalability of chip multipr...
Network-on-chip (NoC) can improve the performance, power efficiency, and scalability of chip multipr...
Optical networks-on-chip (ONoCs) are emerging communication architectures that can potentially offer...
Optical network-on-chip (ONoC) is an emerging communication architecture for manycore systems due to...
Multiprocessor systems-on-chip show a trend toward integration of tens and hundreds of processor cor...
Optical network-on-chip (ONoC) architecture offers ultrahigh bandwidth, low latency, and low power d...
Communication contention and thermal susceptibility are two potential issues in optical network-on-c...
In this paper, we for the first time utilize the micro-ring resonators (MRs) in optical networks-on-...
Network-on-chip (NoC) can improve the performance, power efficiency, and scalability of multiprocess...
Three dimensional Networks-on-Chip (3D NoCs) have attracted a growing interest to solve on-chip comm...
Three dimensional (3D) integration technologies have a smaller footprint area of chip compared to th...
We propose 3D mesh-based optical network-on-chip (ONoC) based on a novel low-cost 66 optical router,...
The performance of multiprocessor systems, such as chip multiprocessors (CMPs), is determined not on...
Optical network on chip is an emerging research topic, which can provide low latency and high bandwi...
The performance of multiprocessor systems, such as chip multiprocessors (CMPs), is determined not on...
Network-on-chip (NoC) can improve the performance, power efficiency, and scalability of chip multipr...
Network-on-chip (NoC) can improve the performance, power efficiency, and scalability of chip multipr...
Optical networks-on-chip (ONoCs) are emerging communication architectures that can potentially offer...
Optical network-on-chip (ONoC) is an emerging communication architecture for manycore systems due to...
Multiprocessor systems-on-chip show a trend toward integration of tens and hundreds of processor cor...
Optical network-on-chip (ONoC) architecture offers ultrahigh bandwidth, low latency, and low power d...
Communication contention and thermal susceptibility are two potential issues in optical network-on-c...
In this paper, we for the first time utilize the micro-ring resonators (MRs) in optical networks-on-...
Network-on-chip (NoC) can improve the performance, power efficiency, and scalability of multiprocess...
Three dimensional Networks-on-Chip (3D NoCs) have attracted a growing interest to solve on-chip comm...
Three dimensional (3D) integration technologies have a smaller footprint area of chip compared to th...