Dielectric quality of 3D capacitor embedded in through-silicon via (TSV)

The concept of 3D capacitor embedded in TSV has been proposed recently to achieve ultrahigh capacitance density (up to 5,621.8 nF/mm2). This paper aims to investigate the effects of trench sidewall roughness and electrode deposition method on the dielectric quality of the 3D capacitor embedded in TSV. The test vehicles of 3D embedded capacitors were designed and fabricated with variations, which were the combinations of: (a) two options of trench sidewall roughness (30 and 290 nm) and (b) three options of electrode deposition methods (sputtering, ALD with air exposure, and ALD without air exposure). For test vehicles with different sidewall roughness but the same electrode deposition method, insignificant change of the leakage current density and dielectric strength can be observed in their J-E plots. Despite thicker dielectric layer, the leakage current density of sputtering test vehicles becomes higher than their ALD counterparts at bias greater than 3.5 MV/cm and dielectric strength ends up lower (∼7.8 vs. >9 MV/cm). Therefore, sputtering is found not suitable for the fabrication of high performance 3D embedded capacitor. Besides, the elimination of air exposure during the process of ALD test vehicles helps suppress the leakage current density when the bias is greater than 4 MV/cm: e.g. it drops from 2.78×10-2 to 4.83×10-5 A/cm2 at 8 MV/cm. Moreover, C-V characterization results suggest that the dielectric composition and the total amount of trapped charges become instable for the test vehicles with rough sidewall (290 nm), whereas they are consistent for the test vehicles with smooth sidewall (30 nm). These findings can provide valuable information for performance optimization and long-term reliability assessment of 3D capacitor embedded in TSV.Agency for Science, Technology and Research (A*STAR)Accepted versionThis work is supported by Agency for Science, Technology and Research (A*STAR) under Individual Research Grant #A1783c0004