Compact modeling of high voltage transistors

Double-diffused Metal Oxide Semiconductor (DMOS) transistors are widely used in silicon based High-Voltage (HV) and Radio Frequency (RF) integrated circuits. Conceptually, the device can be viewed as a series connection of conventional MOSFET and a lightly doped drift resistor. High voltage effects such as quasi-saturation and impact ionization can be seen on the IV characteristics of these devices but not easily captured with a simple sub-circuit. Thus an accurate, efficient and robust compact model for DMOS transistor is both essential and challenging. In order to reduce computational time and increase model robustness, we are using a novel approach to explicitly solve DMOS internal drain voltage and its terminal current. In the proposed compact model, we divide the DMOS into the channel and the drift region. The channel region current is based on explicitly calculated surface potential, and the drift region current is based on a unified regional resistance expression. By simplifying the two expressions and applying Kirchhoff Current Law (KCL) at the internal drain, we are able to obtain the voltage at the internal drain and, hence the terminal current. A few mathematical manipulations are carried out to make sure a valid solution is always obtainable, and curve smoothness is ensured on high-level derivatives. In addition, impact ionization effect is included in this compact model. With the explicitly calculated internal drain voltage, we are able to formulate substrate current based on impact ionization effect in both saturation and quasi-saturation modes. After extracting model parameters, this compact model shows excellent agreement with TCAD and experimental data. In addition, the internal drain voltage calculation is verified with TCAD simulation, which ensures a physical description of the device operation. In the last section, we also demonstrate an application of this compact model in the study of statistical variability of DMOS devices, and its benefit in the area of device optimizations.Doctor of Philosophy (EEE