Low power 32-bit full adders in 65nm CMOS technology

The exponential growth in laptops, mobiles and other portable electronic systems has intensified the research in low-power consumption and hence energy-efficient has become one of the important parameter for portable electronic products. In energyconstrained systems, low power design is required for extending battery lifetime. Therefore, reducing power has become an important criterion in the design of digital circuits. There are various methods to reduce power consumption like supply voltage scaling, switching activity reduction, architectural techniques and device sizing. Out of all these methods, one of the most successful is supply voltage scaling which considerably reduces both static and active components of power consumption. Operating in the near-threshold region is an example of extreme case of supply voltage scaling where the supply voltage is reduced below/to near the threshold voltage of the transistor. It has been proved by extensive research that operating in near-threshold region; transistors consume minimum energy per operation. But operating in nearthreshold region comes at the expense of reduced circuit speed. So in areas where power consumption is primary and speed is secondary concern, operating in near-threshold region is very useful. In this project, emphasis has been given on full adder's operation in near-threshold region. The adder is one of the most critical components of a processor. The system's performance is affected by full adder as a whole. Previous full adder designs have been extensively studied. Emphasis has also been given on XOR-XNOR gates which forms the backbone of full adder logic. Simulations of different XOR-XNOR designs and full-adders upto 32-bit at supply voltages as low as 0.6 V have been done in Cadence environment using TSMC 65nm CMOS technology.Master of Science (Electronics