RRAM Device Performances under Capacitive-Enhanced Current Programming Scheme

International audienceEmbedded resistive random access memories (RRAM) are commonly written using voltage programming scheme. In this work, we study the device performance under an alternative programming approach. Utilizing the parasitic line capacitance combined with a current source, this scheme lowers the required programming current by a factor of 10 for a given conductance level. This effectively reduces writing energy and alleviates constraints on integration density due to electromigration and IR drop. The proposed scheme is demonstrated on 130 nm CMOS technology. The measurements show a low raw bit failure rate of 5.10-5 through 200k cycles. The read margin can be widened up to 25 µA using a write-verify strategy. These metrics highlight the efficiency of the proposed scheme with respect to the conventional voltage techniques