A 3.6 Gigasample/s 5 bit analog to digital converter using 0.3 mu m AlGaAs-HEMT technology

A 0.3 mu m AlGaAs-HEMT technology was used to develop a high speed Analog to Digital Converter (ADC). The 5 bit converter based on a parallel architecture, operates up to a 3.6 GHz sampling rate. Excellent dynamic performance was achieved by an optimized comparator design and careful layout of the signal and clock lines. Each comparator is preceeded by a preamplifier to enhance its sensitivity and to minimize clock kickback. Using source follower buffers at the input, a very linear input capacitance was achieved. Thus the ADC's overall input capacitance is voltage independant