The design and performance of a 28 - 51 GHz dynamic frequency divider based on pseudomorphic Alsub0.2Gasub0.8As/Insub0.25Gasub0.75As MODFETs with 0.15Mym mushroom-shaped gates are presented. The circuit has a power consumption of approximately equal to 440 mW and a chip area of approximately equal to 200 x 220 My square meter
The design and performance of a dynamic frequency divider was presented. This digital IC demonstrate...
Design of a digital dynamic divider in SiGe bipolar technology is presented in this paper. The propo...
Abstract A divide-by-2 frequency divider circuit was designed using 22-nm CMOS FD-SOI technology. T...
A divide-by-two dynamic frequency divider based on enhancement and depletion 0.2 mu m gate length ps...
Two static and two dynamic frequency dividers based on enhancement and depletion 0.2-mu m gate lengt...
The design and performance of a dynamic divider by four based on a 100 nm metamorphic enhancement HE...
A programmable frequency divider for the use in a fractional-N frequency synthesizer is presented. T...
A frequency devider based on AlGaAs/GaAs/AlGaAs quantum well FETs with 0.2 micrometer gate length ha...
Funding Information: This research has been financially supported by Academy of Finland (grant 24302...
Abstract—In this paper we present the design of a pro-grammable frequency divider in 28 nm FD-SOI CM...
Abstract- A low power and high speed 8/9 CMOS programmable dynamic frequency divider has been design...
High speed frequency dividers are critical parts of frequency synthesisers in wireless systems. Thes...
A programmable frequency divider operating at input frequencies from DC to 80 GHz for the use in fra...
A divide-by-four circuit divides frequencies from 31GHz to 41GHz at input signal amplitudes ≤0.5Vpp....
Based on a 100 nm metamorphic HEMT process with 220 GHz transit frequency fT an optimised dynamic 2:...
The design and performance of a dynamic frequency divider was presented. This digital IC demonstrate...
Design of a digital dynamic divider in SiGe bipolar technology is presented in this paper. The propo...
Abstract A divide-by-2 frequency divider circuit was designed using 22-nm CMOS FD-SOI technology. T...
A divide-by-two dynamic frequency divider based on enhancement and depletion 0.2 mu m gate length ps...
Two static and two dynamic frequency dividers based on enhancement and depletion 0.2-mu m gate lengt...
The design and performance of a dynamic divider by four based on a 100 nm metamorphic enhancement HE...
A programmable frequency divider for the use in a fractional-N frequency synthesizer is presented. T...
A frequency devider based on AlGaAs/GaAs/AlGaAs quantum well FETs with 0.2 micrometer gate length ha...
Funding Information: This research has been financially supported by Academy of Finland (grant 24302...
Abstract—In this paper we present the design of a pro-grammable frequency divider in 28 nm FD-SOI CM...
Abstract- A low power and high speed 8/9 CMOS programmable dynamic frequency divider has been design...
High speed frequency dividers are critical parts of frequency synthesisers in wireless systems. Thes...
A programmable frequency divider operating at input frequencies from DC to 80 GHz for the use in fra...
A divide-by-four circuit divides frequencies from 31GHz to 41GHz at input signal amplitudes ≤0.5Vpp....
Based on a 100 nm metamorphic HEMT process with 220 GHz transit frequency fT an optimised dynamic 2:...
The design and performance of a dynamic frequency divider was presented. This digital IC demonstrate...
Design of a digital dynamic divider in SiGe bipolar technology is presented in this paper. The propo...
Abstract A divide-by-2 frequency divider circuit was designed using 22-nm CMOS FD-SOI technology. T...