Optimized FPGA-based hardware emulation by using partial runtime reconfiguration (pRTR)

We propose a novel conception to optimize the resource utilization of FPGA-based hardware emulation. The main purpose is to exploit methods of partial dynamic reconfiguration (pRTR) which enable run-time multiplexing of design components. To divide the circuit into independet components, we have utilized a partitioning approach using generic synthesis. This method is able to meet particular requirements such as the number of logic cells, bandwidth of bus structures or dataflow characteristics. In addition, our conception for optimized emulation is tailored to state-of-the-art FPGA platforms providing an embedded PowerPC (e.g. VirtexII-pro, Virtex4). Therefore, we can realize a real-time solution to schedule the reconfiguration of design components (enabling a clock-precise control of the emulator). Finally, all I/O signals of design components in particular (re-)configuration phases, are processed for emulation by a generic simulator