Development of a 3D wafer-level re-routing, using dielectric lamination technology

Technical developments in wafer level packaging of electrical devices are to be in line with the more general packaging trends like volume and footprint reduction. The realization of highly miniaturized System in Package (SiP) or thin stackable packages containing active and passive devices, the formation of 3-D interconnection patterns, making interconnection through the silicon wafer, connecting top to bottom, requires new or improved manufacturing technologies. This paper will present the approaches for the technological realization of 5x5mm² ?eGrain? prototypes based on Berkeley structures. These ?eGrain? structures combine different functional layers, to be realized in the smallest size, to achieve the intended overall dimension. Therefore the use of the surface of the silicon wafer as a substrate for the volume components (R, L, C) is needed. To realize this approach, a re-routing in the third dimension is a major challenge. As a solution for 3D interconnects the continuous development of the Via-in-Via technology will be presented. This technology utilizes the formation of via holes through the silicon wafer and forming an electrical contact from the front- to the backside. For the realization of these vias a laser drilling process is used. To understand the interaction between this drilling process and the silicon, studies concerning the via diameter and density where done and will be discussed in depth. To produce the electrical contact it is necessary to isolate the walls of the vias. In this new approach of the Via-in-Via technology, the wafer containing vias in the silicon is vacuum laminated, using a RCC material for filling the vias and providing the copper needed for the conductor lines. A second via will be opened in the epoxy material by laser drilling, followed by an electroless metallization process, realizing the electrical contact. The formation of the conductor lines can be realized either by structuring a photo resist mask and etching of the copper or by laser structuring of the copper. The challenges, processes and results will be discusses in detail. For the evaluation of the electrical properties of the 3D interconnect a test die, containing daisy-chain structures and realizing 20 three dimensional interconnects per die, was chosen. Finally the results of the realization of the test vehicle will be presented