Investigations on via geometry and wetting behavior for the filling of through silicon vias by copper electro deposition

The background of this paper is the fabrication of Through Silicon Vias (TSV) for three-dimensional chip stacking. At first an adapted etching process is presented. Vias with a cross sectional area of approx. 3x10 square micron and 50 - 70 micron depth were etched. Those vias have a V-shaped entrance that is aimed to prevent a pinch-off at the via-top and a void formation during the subsequent filling process. For a better filling performance a pre-treatment of the vias is necessary, too. Therefore the wetting behavior of Cu-CVD and Cu-PVD layers as well as Au-PVD layers that have undergone several pre-treatments was investigated by contact angle measurements. Moreover two plating chemistries were investigated regarding their impact on the wetting. Copper electro deposition experiments have been performed using DC and Pulse-Reverse (PR) currents and two commercially available electrolyte systems. In this experiment the beneficial effect of the V-shaped vias could be shown as well as the impact of several pre-treatments