A 1:2 demultiplexer (DEMUX) circuit has been successfully designed and manufactured using high-speed InP/InGaAs DHBT technology. The 1:2 DEMUX features proper operation at data rates up to 120 Gbit/s. At this data rate, a minimum eye opening of 150 mVpp is required at the data input of the IC for generating 60 Gbit/s output data with impeccable eye opening and a voltage swing of 530 mVpp
This letter reports the potential of an InP-based double-heterojunction bipolar transistor (DHBT) us...
An ultrahigh speed 4 bit demultiplexer circuit has been developed and fabricated using a recessed ga...
We report on the development of a double heterojunction bipolar transistor (DHBT) technology on InP ...
In this paper, a 100 Gbit/s fully integrated clock and data recovery (CDR) circuit with 1:2 demultip...
In this paper we present the design and optimization of decision and DEMUX circuits fabricated in a ...
This paper presents a monolithically integrated clock and data recovery (CDR) circuit with 1:2 demul...
Key components and architecture options are being actively investigated to realize next generation t...
In this paper, we report a manufacturable InP DHBT technology, suitable for medium scale mixed-signa...
It is now clear that 112-Gb/s data rate is the next step in the network evolution (100-Gb/s Ethernet...
An 80 Gbit/s monolithically integrated clock and data recovery (CDR) circuit with 1:2 demultiplexer ...
In this paper, we report the achieved performance of devices and integrated circuits (ICs) using a m...
We report on design and test of state-of-the-art building blocks for a 100 Gb/s demonstrator system:...
International audienceWe report on an Indium Phosphide (InP) double heterojunction bipolar transisto...
In this paper we present two ICs fabricated in InP DHBT technology and devoted to 43 Gbit/s and over...
In this work, up to 80 Gbit/s monolithically integrated clock and data recovery (CDR) circuits with ...
This letter reports the potential of an InP-based double-heterojunction bipolar transistor (DHBT) us...
An ultrahigh speed 4 bit demultiplexer circuit has been developed and fabricated using a recessed ga...
We report on the development of a double heterojunction bipolar transistor (DHBT) technology on InP ...
In this paper, a 100 Gbit/s fully integrated clock and data recovery (CDR) circuit with 1:2 demultip...
In this paper we present the design and optimization of decision and DEMUX circuits fabricated in a ...
This paper presents a monolithically integrated clock and data recovery (CDR) circuit with 1:2 demul...
Key components and architecture options are being actively investigated to realize next generation t...
In this paper, we report a manufacturable InP DHBT technology, suitable for medium scale mixed-signa...
It is now clear that 112-Gb/s data rate is the next step in the network evolution (100-Gb/s Ethernet...
An 80 Gbit/s monolithically integrated clock and data recovery (CDR) circuit with 1:2 demultiplexer ...
In this paper, we report the achieved performance of devices and integrated circuits (ICs) using a m...
We report on design and test of state-of-the-art building blocks for a 100 Gb/s demonstrator system:...
International audienceWe report on an Indium Phosphide (InP) double heterojunction bipolar transisto...
In this paper we present two ICs fabricated in InP DHBT technology and devoted to 43 Gbit/s and over...
In this work, up to 80 Gbit/s monolithically integrated clock and data recovery (CDR) circuits with ...
This letter reports the potential of an InP-based double-heterojunction bipolar transistor (DHBT) us...
An ultrahigh speed 4 bit demultiplexer circuit has been developed and fabricated using a recessed ga...
We report on the development of a double heterojunction bipolar transistor (DHBT) technology on InP ...