FPGA-based runtime adaptive multiprocessor approach for embedded high performance computing applications

Embedded high performance computing applications, like for example image processing in surveillance systems, are very compute intensive due to the complexity of the algorithms. Additionally to the computing intensive data processing, the power consumption for such systems needs to be minimized in order to keep them lightweight and mobile operational. One solution for achieving these goals is to exploit hardware parallelism for acceleration purposes on reconfigurable hardware, like Field Programmable Gate Arrays (FPGA). Due to the increase of performance, the clock speed can be reduced, which leads to a reduced power consumption in comparison to traditional processor-based approaches. A challenging task until today is the programming of these devices e.g. with standardized tools or languages like e.g. C. There exist C-to-FPGA tools that ease the programming of these systems, but they do not handle the communication with the environment, e.g. camera interfaces, PCI-interfaces, etc. This still has to be designed in time consuming and handcrafted work. Also the aforementioned tools still have some restriction on the input language. The novel approach in the presented work is to combine processors in a multiprocessor architecture on FPGA for high performance computing applications. This solution combines the flexibility of FPGAs and the high-level programming paradigms of multiprocessor systems and can be seen as a meet-in-the middle solution. This holistic approach is called RAMPSoC (Runtime Adaptive MPSoC) and combines a novel hardware architecture, consisting of heterogeneous processing elements connected over a novel heterogeneous Network-on-Chip, with a user-guided design methodology and a new runtime resource management system