Impact of the storage layer charging on random telegraph noise behavior of sub-50nm charge-trap-based TANOS and floating-gate memory cells

With the transistor scaling in the deca-nanometer range the impact of Random Telegraph Noise (RTN) on device reliability has significantly increased. Randomly occuring capture and emission of electrons in Si/SiO2 interface traps is causing a threshold voltage Vth) fluctuation and thereore instable device operation. The RTn impact on reliability is more prominent on non -volatile memory cells as compared to digital CMOS circuits due to the increased bottom oxide thickness and the commonly used multi-level operation