A silicon-interposer technology with high density Cu-filled TSVs and Cu-based redistribution layers was realized. Test structures in a process control module were used for electrical characterization
For considerations of stress reduction HAR-TSVs were only partially filled with copper. A comparison...
Flip chip is one of the packaging techniques for high-performance components. There is a greater dem...
In this paper, Air-gaped Si interconnection for TSV interposer is presented, it's low stress du...
This manuscript contains a detailed description of the fabrication steps for processing of silicon i...
This paper proposes an interposer fabrication methods with annular copper through-silicon via (TSV) ...
In this paper, a thick TSV interposer with integrated inductor, micro-strip and coplanar waveguides(...
Because of Moore's (scaling/integration) law, the Cu/lowk silicon chip is getting bigger, the pin-ou...
A through silicon interposer (TSI) fabrication process and detailed characterization and measurement...
A through silicon interposer (TSI) fabrication process and detailed characterization and measurement...
For the electrochemical filling of through silicon vias (TSVs) the geometry of these vias as well as...
The fabrication of redistribution layer (RDL) for TSV 3D integration and its optimization are presen...
In this paper Microchannel embedded TSV interposer is presented, process development is proposed wit...
Redistribution layer (RDL) is necessary for electric interconnection of TSV-based 3D stacking applic...
In this paper Microchannel embedded TSV interposer is presented, process development is proposed wit...
In this paper, electrical characteristic of TSV (Through Silicon Via) is analyzed. Firstly, equivale...
For considerations of stress reduction HAR-TSVs were only partially filled with copper. A comparison...
Flip chip is one of the packaging techniques for high-performance components. There is a greater dem...
In this paper, Air-gaped Si interconnection for TSV interposer is presented, it's low stress du...
This manuscript contains a detailed description of the fabrication steps for processing of silicon i...
This paper proposes an interposer fabrication methods with annular copper through-silicon via (TSV) ...
In this paper, a thick TSV interposer with integrated inductor, micro-strip and coplanar waveguides(...
Because of Moore's (scaling/integration) law, the Cu/lowk silicon chip is getting bigger, the pin-ou...
A through silicon interposer (TSI) fabrication process and detailed characterization and measurement...
A through silicon interposer (TSI) fabrication process and detailed characterization and measurement...
For the electrochemical filling of through silicon vias (TSVs) the geometry of these vias as well as...
The fabrication of redistribution layer (RDL) for TSV 3D integration and its optimization are presen...
In this paper Microchannel embedded TSV interposer is presented, process development is proposed wit...
Redistribution layer (RDL) is necessary for electric interconnection of TSV-based 3D stacking applic...
In this paper Microchannel embedded TSV interposer is presented, process development is proposed wit...
In this paper, electrical characteristic of TSV (Through Silicon Via) is analyzed. Firstly, equivale...
For considerations of stress reduction HAR-TSVs were only partially filled with copper. A comparison...
Flip chip is one of the packaging techniques for high-performance components. There is a greater dem...
In this paper, Air-gaped Si interconnection for TSV interposer is presented, it's low stress du...
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