Enabling system level simulation of 3D integrated systems

3D-integration is a suitable approach to reduce the size of all-electronic or micro electro mechanical systems (MEMS). However, this new strategy does not only challenge technology but also design procedures. Due to the compact arrangement of components, especially thermal issues and the occurrence of eletrical parasitics have to be taken into account during the design process. As these effects influence the complete system, a system level simulation is required. In this paper we present an approach based on behavioral modelling and partly model order reduction (MOR). Behavioral models can be translated to different description languages preferred by the designer and thus facilitate system level simulation. We illustrate our procedure using an example 3D-integrated system. By means of MOR we reduce the size of its thermal finite element model significantly and translate it to Verilog-A. As a second approach to generate behavioral models we develop an equivalent network model for through silicon vias based on the simulated transfer function