Intrinsic MOSFET leakage of high-k peripheral DRAM devices: Measurement and simulation

The gate leakage (I Gate, table 1) is reduced compared to the conventional 65nm process with SiON dielectric (Fig. 2). The leakage current due to direct tunneling is simulated using the CET as fitting parameter. High-k PFETs with an oxide extension spacer show a decrease in leakage density with reducing channel length, due to an average CET increase of 1Å (Fig. 3). Most likely unintended oxidation of the interlayer at the gate edge by oxygen supply through the spacer causes the CET increase (Fig. 1). The phenomenon is avoided using a nitride extension spacer. But nitride spacers at the inner gate edge are known to lead to increased gate induced drain leakage (GIDL) [8]. A dual oxide nitride extension spacer is sufficient to prevent unintended gate edge oxidation (Fig. 3)