Verification of E-Beam direct write integration into 28nm BEOL SRAM technology

Electron beam direct write lithography (EBDW) potentially offers advantages for low-volume semiconductor manufacturing, rapid prototyping or design verification due to its high flexibility without the need of costly masks. However, the integration of this advanced patterning technology into complex CMOS manufacturing processes remains challenging. The low throughput of today’s single e-Beam tools limits high volume manufacturing applications and maturity of parallel (multi) beam systems is still insufficient [1,2]. Additional concerns like transistor or material damage of underlying layers during exposure at high electron density or acceleration voltage have to be addressed for advanced technology nodes. In the past we successfully proved that potential degradation effects of high-k materials or ULK shrink can be neglected and were excluded by demonstrating integrated electrical results of 28nm node transistor and BEOL performance following 50kV electron beam dry exposure [3]. Here we will give an update on the integration of EBDW in the 300mm CMOS manufacturing processes of advanced integrated circuits at the 28nm SRAM node of GLOBALFOUNDRIES Dresden. The work is an update to what has been previously published [4]. E-beam patterning results of BEOL full chip metal and via layers with a dual damascene integration scheme using a 50kV VISTEC SB3050DW variable shaped electron beam direct writer at Fraunhofer IPMSCNT are demonstrated. For the patterning of the Metal layer a Mix & Match concept based on the sequence litho - etch -litho -etch (LELE) was developed and evaluated wherein several exposure fields were blanked out during the optical exposure. Etch results are shown and compared to the POR. Results are also shown on overlay performance and optimized e-Beam exposure time using most advanced data prep solutions and resist processes. The patterning results have been verified using fully integrated electrical measurement of metal lines and vias on wafer level. In summary we demonstrate the integration capability of EBDW into a productive CMOS process flow at the example of the 28nm SRAM technology node