Comparative Study of Parallel Multipliers Based on Recoding Techniques

A 5-bit recoding scheme reduces the number of partial products by a factor of four in an array multiplier, but at the same time increases the complexity of recoding and partial products generation process. There is no concrete evidence yet , about efficiency or deficiency for applying 5-bit recoding. In this study, we compare the area-time performance of the VLSI implementation of 5-bit recoding array multipliers to its 3-bit recoding counterparts. Conditions in which a 5-bit multipliers is more efficient in terms of area and propagation time than that of a 3-bit recoding one are derived for given word lengths. We then present an example 5-bit recoding circuit design and its VLSI layout that yields the area-time efficiency