Efficient FPGA realizations based on AND /XOR expressions

In this dissertation, we propose an AND/XOR-based technology mapping method for field programmable gate arrays (FPGAs). Due to the fixed size of the programmable blocks in an FPGA, decomposing a circuit into sub-circuits with appropriate number of inputs can achieve excellent implementation efficiency. Specifically, the proposed technology mapping method is based on Davio expansion theorem to decompose a given Boolean circuit. The AND/XOR nature of the proposed method allows it to operate on XOR intensive circuits, such as error detecting/correcting, data encryption/decryption, and arithmetic circuits, efficiently. We design three different approaches: (1) Direct Approach, (2) AND/XOR Direct, and (3) Proposed Davio Approach and conduct experiments using MCNC benchmark circuits. First, we formulate the parity prediction circuits for the MCNC benchmark circuits. Proposed Davio Approach is superior to the conventional methods for parity prediction circuits in terms of both speed and area. When using Proposed Davio Approach, the number of CLBs is reduced by 67.6% (speed-optimized) and 57.7% (area-optimized), total equivalent gate counts are reduced by 65.5%, maximum combinational path delay is reduced by 56.7%, and maximum net delay is reduced by 80.5% compared to Direct Approach. We then apply the proposed method to the benchmark circuits themselves and found that the proposed method is still quite competitive for achieving realization efficiency in FPGAs