Early estimates of the economic impacts during microelectronics product design

An investigation was performed to develop a set of detailed analytical cost models to estimate the economic impact for microelectronics IC product design alternatives. The Cost of Ownership (COO) model was introduced and extended to each cost domain of microelectronics product development cycles. The cost models were developed for each essential design alternative in each cost domain. In the domain of test, the cost models for typical DFT solutions of Scan and BIST were built. In the domain of fabrication, the cost models of the popular optical lithography technologies of DUV (ArF, KrF) and i-line were developed. In the case of design, ASIC/gate arrays design process with respect to FPGA/PLD design alternative was modeled for the cost estimate. By applying the methodology developed in this research, three software-based tools in each cost domain were developed in JavaScript language to quantitatively evaluate cost/time criteria of design alternatives during the early stage of product design to aid the decision making. With such tools, designers can analyze what-if scenario quickly and accurately, given good input data. A design guideline was formulated from results of sensitivity analyses of cost models in each domain. The case study of design alternatives in each domain was carried out using the industry standard data with the software tools. The result of the case studies matches the realistic data and rules-of-thumb as seen in the industry