Automated test control block generation and minimization

At Philips Research Laboratories a silicon compiler for digital signal processor applications has been developed. It generates hierarchical IC designs composed of functional building blocks. The ICs are tested following the macro test strategy. Each building block has its own test plan; a procedure to access it for test purposes. To save bonding pads the control signals for the tests can be generated by an on-chip Test Control Block (TCB). Both the TCB and the test plans for the building blocks can be represented by finite state machines. This report presents a method to merge the test plans of the building blocks into one minimal finite state machine, in order to minimize silicon area overhead caused by the TCB. This merging is found to involve a specific combination of degrees of freedom, that causes both the problem to be NP-hard and algorithms in the literature inadequate to solve it. Therefore dedicated heuristic algorithms have been developed and implemented in software called ‘‘MAF’’. ‘‘MAF’’ turned out to be competitive to manual minimization. This software is part of an enabling technology to support multi-level TCB merging in a macro-test environment