Analysis, Modelling and Improvements of a Capacitance-to-Digital Converter for Sensor Applications

The work focused on the ENS220 chip produced by ScioSense, that is a chip used for temperature and ambient pressure measurement. This is a state-of art product in terms of achievable resolution; as a matter of fact for the pressure measurement a 24 bit ENOB is guaranteed. The goal of the thesis was to verify if it was possible to improve the pressure sensor performance, finding out if it was feasible to achieve a comparable resolution with a lower power consumption. The aim was to understand if the architecture was theoretically compatible with a lower voltage supply, and quantify any degradations of the constituent components, in order to identify the components that require a subsequent re-design to be compatible with the circuit expected performance. To make this, the pressure sensor interface was analysed observing its schematic: the circuit is based on a Capacitance-to-Digital Converter (CDC) employing a 3rd order Delta-Sigma configuration with a switched-capacitor implementation. The Delta-Sigma converter is implemented with a cascaded 2+1 structure, and its block diagram can be derived, obtaining a Chain of Integrators with Distributed Feedbacks and Feedforwards configuration. After a first phase of Delta-Sigma theory deepening, the work focused on building a Simulink model of the real circuit, based on the block diagram of the circuit. The goal was to have a model easier and quicker to simulate and at the same time it had to fit as much as possible the real circuit behaviour. Firstly an ideal model was considered and validated, while subsequently the main non-idealities of the circuit constituent components were added, in particular hysteresis and offset for the comparators, and slew rate, noise, saturation limits and more, for the operational amplifiers in their integrator configuration. These non-idealities were taken into account using a MATLAB functions library, with some modifies for the case under consideration; this library is specific to simplify the design of Delta-Sigma ADCs and allows to insert the components parameters in a matrix defined in the workspace, by means of a MATLAB script. The non-idealities parameters were measured using some Cadence testbenches, considering also PVT variations and mismatch in order to obtain a realistic estimation of the components performance; in this way it is possible to more accurately model the real performance of the chip produced by the foundry. Once introduced the circuit non-idealities, the Simulink model was verified and validated in an exhaustive way, by means of a performance evaluation in terms of the effective number of bits (ENOB) and Signal-to-Noise Ratio (SNR), measured using the Simulink spectrum analyzer. Furthermore the obtained Simulink waveforms were compared with those obtained by the top level Cadence simulation of the ENS220, and observing that their trends were qualitatively and quantitatively similar to what was obtained from Simulink. The top level circuit was simulated employing an Analog Mixed-Signal (AMS) simulator, with a stimulus written in Verilog-AMS HDL that was properly modified. In order to equivalently stimulate both the Simulink model and the Cadence circuit, a sinusoidal input capacitance was implemented in Cadence, using a Verilog-A HDL code. The last part of thesis focused on measuring the performance of the components with a lower voltage supply, and the consequent necessary modifies of the voltage supply scaling on the Simulink model. In this phase the new values of the components non-idealities were measured considering PVT variations and mismatch, and inserted in the corresponding Simulink model with a similar procedure. The performance of the CDC with a lower supply was compared with the original CDC finding some issues on the worst case values of the parameters; the chip critical components were identified, in view of a future re-design operation. Finally, some considerations about possible modifies to the adopted architecture topology were done, finding better performance changing a feedforward sign and increasing the feedback values