Receiver Performance Simulation : System Verification for GSM Receiver

The purpose of this thesis is to build and then optimize a simulation environment for the GSM / EDGE / WCDMA receiver in the RF Asics. The system generally consists of two blocks: an Agilent Advanced Design System (ADS) controlled system core and Simulation Environment System for Verification and Design (SEVED). The signal is generated by SEVED and directed into the system core, where the receiver under test is located. Signal output of the receiver is then directed back into SEVED for bit error rate calculations. Therefore the performance of the receiver can be evaluated