AASH: Asymmetry-aware scheduler for hypervisors

Asymmetric many-core processors (AMPs) consist of cores varying in size, frequency, power consumption and performance, all exposing the same instruction-set architecture. Since this architecture exploits both powerful fast cores and simple slow cores, it can offer a potential speedup that is much greater than symmetric architecture. This work for the first time implements simple changes to the hypervisor scheduler, required to make it asymmetry-aware, and evaluates the benefits and overheads of these asymmetry-aware mechanisms. Our results indicate significant performance improvements, reaching up to 36% in our experiments. Most performance improvements are derived from the fact that an asymmetry-aware hypervisor ensures that the fast cores do not go idle before slow cores and from the fact that it maps virtual cores to physical cores for asymmetry-aware guests according to the guest’s expectations. Other benefits from asymmetry awareness are fairer sharing of computing resources among VMs and more stable execution time