Reduction Of Architecture Vulnerability Factor Using Modified Razor Flipflops

Research has shown that microprocessors and structures of the microprocessors are vulnerable to alpha Single Event Upsets that affect program correctness and reliability. In this thesis, we have explored the use of Modified Razor flip-flops in the microprocessor to increase the overall reliability of the microprocessor. We have adopted Architecturally Correct Execution (ACE) time based techniques to measure the Architecture Vulnerability Factor (AVF) of high performance microprocessors and their internal structures using the SPEC 2000 integer benchmarks. We have computed the reduction in AVF with the introduction of Modified Razor flip-flops for various combinations of bit-fields that have high vulnerability. However, introduction of Modified Razor flip-flops results in higher area requirement on the die and higher power consumption. We have identified the most cost-effective solution by identifying the fields of these microarchitectural structures - where Modified Razor flip-flops are introduced - that result in the highest percentage decrease in AVF per unit area-power product