Performance of On-Line Learning Methods in Predicting Multiprocessor Memory Access Patterns

  • Sakr, Majd F.
  • Levitan, Steven P.
  • Chiarulli, Donald M.
  • Horne, Bill G.
  • Giles, C. Lee
Publication date
October 1998

Abstract

Shared memory multiprocessors require reconfigurable interconnection networks (INs) for scalability. These INs are reconfigured by an IN control unit. However, these INs are often plagued by undesirable reconfiguration time that is primarily due to control latency, the amount of time delay that the control unit takes to decide on a desired new IN configuration. To reduce control latency, a trainable prediction unit (PU) was devised and added to the IN controller. The PU's job is to anticipate and reduce control configuration time, the major component of the control latency. Three different on-line prediction techniques were tested to learn and predict repetitive memory access patterns for three typical parallel processing applicat...

Extracted data

Loading...

Related items

Predicting Multiprocessor Memory Access Patterns with Learning Models
  • M. F. Sakr
January 1997

A neural network based technique is introduced which hides the control latency of reconfigurable int...

Online prediction of multiprocessor memory access patterns
  • M. E. SAKR
  • C. L. GILES
  • S. P. LEVITAN
  • B. G. HORNE
  • D. M. CHIARULLI
  • MAGGINI, MARCO
January 1996

A neural network based technique is introduced which hides the control latency of reconfigurable int...

Predictive control of opto-electronic reconfigurable interconnection networks using neural networks
  • M. F. SAKR
  • S. P. LEVITAN
  • C. L. GILES
  • B. G. HORNE
  • D. M. CHIARULLI
  • MAGGINI, MARCO
January 1995

Opto-electronic reconfigurable interconnection networks are limited by significant control latency w...

We use cookies to provide a better user experience.