SpaceWire Router

A SpaceWire network comprises SpaceWire links, nodes and routers. The nodes are the functional units that wish to use the onboard communication services of the SpaceWire network and are fitted with one or more SpaceWire interfaces. These units are connected together directly using point-to-point SpaceWire links or indirectly via SpaceWire routers. SpaceWire interfaces, links and routers are the three elements of a SpaceWire network. This paper explains the operation of a SpaceWire router and describes the radiation tolerant SpaceWire router ASIC being developed for ESA. A SpaceWire routing switch is able to connect together many nodes, providing a means of routing packets between the nodes connected to it. A SpaceWire routing switch comprises a number of SpaceWire link interfaces and a routing matrix. The routing matrix enables packets arriving at one link interface to be transferred to and sent out of another link interface on the routing switch The radiation tolerant routing switch currently being developed is fully SpaceWire compliant and has the following facilities: Eight SpaceWire ports. Two external parallel ports, each comprising an input FIFO and an output FIFO. A non-blocking crossbar switch connecting any input port to any output port. An internal configuration port accessible via the crossbar switch from the external parallel port or the SpaceWire ports. A routing table accessible via the configuration port which holds the logical address to output port mapping. Control logic to control the operation of the switch, performing arbitration and group adaptive routing. Control registers than can be written and read by the configuration port and which hold control information e.g. link operating speed. An external time-code interface comprising tick_in, tick_out and current tick count value. Internal status/error registers accessible via the configuration port External status/error signals This paper describes the operation of a SpaceWire Router covering path and logical addressing schemes, priority and arbitration mechanisms, and group adaptive routing. The architecture of the router ASIC is described and the results of initial FPGA implementation and testing reported. The development schedule and expected performance are provided.