A counter architecture for online DVFS profitability estimation

Dynamic voltage and frequency scaling (DVFS) is a well-known and effective technique for reducing power consumption in modern microprocessors. An important concern though when applying DVFS for online energy and power optimizations is to estimate its profitability in terms of performance and energy. Current DVFS profitability estimation approaches however lack accuracy or incur runtime performance and/or energy overhead. This paper proposes a counter architecture for online DVFS profitability estimation on superscalar out-of-order processors. The counter architecture teases apart the fraction of the execution time that is susceptible to clock frequency versus the fraction that is insusceptible to clock frequency. By doing so, the counter architecture can accurately estimate the performance and energy consumption at different V/f operating points from a single program execution. The DVFS counter architecture estimates performance, energy consumption and ED2P within 0.2%, 0.5% and 0.8% on average, respectively, over a 4× frequency range. Further, the counter architecture incurs a limited hardware cost and is an enabler for online DVFS scheduling both at the intra-core as well as at the inter-core level in a multi-core processor