Developing memory templates for high level synthesis compilers

We are investigating parametrized memory templates for use with high level synthesis compilers. Each template would have parameters that reflect important trade-offs made during system design, and can be interfaced with external block random access memory (BRAM). The templates would incorporated in our high level synthesis (HLS) compiler, where the template's parameters are adjusted to the application and hardware. Each template would be designed to suite a different type of application. For example we have already made one template for use with a parallel 'for' loops with no loop dependencies and sequential bodies. In the future, we will develop more templates for other types of 'for' loops. We will enhance the compiler so that it can identify the type of application it is compiling and recommend the template best suited for it. The candidate templates will be selected by first matching them against the application's data access pattern with the final decision made using design space exploration of each candidate to find the one with the best performance characteristics