Protecting prediction arrays against faults

Continuous circuit and wire miniaturization increasingly exert more pressure on the computer designers to address the issue of reliable operation in the presence of faults. Virtually all previous work on processor reliability addresses problems due to faults in architectural structures, such as the register file or caches. However, faults can happen in non-architectural resources, such as predictors and replacement bits. Although non-architectural faults do not affect correctness they can degrade a processor performance significantly and, therefore, may render them as important to deal with as architectural faults. This paper quantifies the performance implications of faults in a line-predictor, and shows that performance can drop significantly when the line-predictor has faulty entries. In particular, a simulation based worst-case analysis of a high-end processor that experiences faults in 1% of the entries in the line-predictor, revealed an average performance degradation of 8% and up to 26%. For solutions we point at no bit-interleaving as a more fault-tolerant design style for prediction arrays and to a hardware protection scheme based on address-remapping. This scheme is able to recover most of the performance loss when up to 5% of the line-predictor entries are faulty and when no faults exist it does not degrade performance