Add to ORKGThe segmented bus is a power-efficient architecture for intra-tile SoC communication, where energy is saved by switching off unused bus segments cycle-by-cycle. We determine the pattern of switch control bits and calculate the cost of transporting them. A test case indicates that the cost is much lower than the gain obtained from the segmentation, and that the prospects of segmented buses remain promising
The main motivation of this work is to investigate techniques to reduce the power consumption inside...
International audienceInterconnects are now considered as the bottleneck in the design of system-on-...
Transitions on high capacitance busses in VLSI systems result in considerable power dissipation. Var...
The segmented bus is a power-efficient architecture for intra-tile SoC communication, where energy i...
Keywords—System-on-Chip, deep sub-micron technology, bus interconnection, segmented bus, power-aware...
The sectioned bus is an energy-optimal architecture for system-on-chip (SoC) communication, where we...
Abstract — This paper1 proposes a bus-segmentation method that efficiently reduces the switched capa...
The concept of bus segmentation has been proposed to minimize power consumption by reducing the swit...
Abstract — The amount of energy consumed for interconnect-ing the IP-blocks is increasing significan...
The communication and memory organization in system on chip are a major source of energy consumption...
In the deep sub-micron domain wires consume more power than transistors. Power Gating for Wires is a...
University of Minnesota Ph.D. dissertation. November 2008. Major: Electrical Engineering. Advisor: G...
The power consumption due to the HW/SW communication on system-level buses represents one of the maj...
[[abstract]]The trend towards distributed, networked embedded systems is changing the way power shou...
The power consumption due to the HW/SW communication on system-level buses represents one of the maj...
The main motivation of this work is to investigate techniques to reduce the power consumption inside...
International audienceInterconnects are now considered as the bottleneck in the design of system-on-...
Transitions on high capacitance busses in VLSI systems result in considerable power dissipation. Var...
The segmented bus is a power-efficient architecture for intra-tile SoC communication, where energy i...
Keywords—System-on-Chip, deep sub-micron technology, bus interconnection, segmented bus, power-aware...
The sectioned bus is an energy-optimal architecture for system-on-chip (SoC) communication, where we...
Abstract — This paper1 proposes a bus-segmentation method that efficiently reduces the switched capa...
The concept of bus segmentation has been proposed to minimize power consumption by reducing the swit...
Abstract — The amount of energy consumed for interconnect-ing the IP-blocks is increasing significan...
The communication and memory organization in system on chip are a major source of energy consumption...
In the deep sub-micron domain wires consume more power than transistors. Power Gating for Wires is a...
University of Minnesota Ph.D. dissertation. November 2008. Major: Electrical Engineering. Advisor: G...
The power consumption due to the HW/SW communication on system-level buses represents one of the maj...
[[abstract]]The trend towards distributed, networked embedded systems is changing the way power shou...
The power consumption due to the HW/SW communication on system-level buses represents one of the maj...
The main motivation of this work is to investigate techniques to reduce the power consumption inside...
International audienceInterconnects are now considered as the bottleneck in the design of system-on-...
Transitions on high capacitance busses in VLSI systems result in considerable power dissipation. Var...