Presented is a 'Redundant Signed Digit' driving scheme for binary weighted D/A conversion. This scheme retains the simplicity of conventional binary weighted D/A conversion, but has greatly improved robustness with regard to parasitic effects, especially when processing signals with a high crest factor. Such signals occur in communication systems that use, e.g. orthogonal frequency-division multiplexing (OFDM). In this case an improvement of 9 dB in Missing Tone Power Ratio performance was measured on a prototype 250 MSample/s circuit implemented in 0.18 mu m CMOS
“This material is presented to ensure timely dissemination of scholarly and technical work. Copyrigh...
A compact current-mode Digital-to-Analog converter (DAC) suitable for biomedical application is repe...
In this thesis, we have explained the different types of DAC (Digital-to-Analog) architectures and t...
Presented is a 'Redundant Signed Digit' driving scheme for binary weighted D/A conversion. This sche...
It is well known that the performance of current steering D/A converters (DACs) is affected by paras...
It is well known that Nyquist DACs suffer from static as well as dynamic errors. In this paper, clas...
Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer...
Abstract—A digital random return-to-zero technique is pre-sented to improve the dynamic performance ...
This thesis describes theoretical and simulation-based work on digital-to-analog conversion ...
In this paper we present a new digital analog converter (DAC) design, based on the binary weighted r...
A 5-bit 2GS/s current-steering D/A converter for ultra-wideband (UWB) transceivers is presented in t...
A 9 bit 11 GS/s DAC is presented that achieves an SFDR of more than 50 dB across Nyquist and IM3 bel...
This paper presents a six-bit current-steering digital-to-analogue converter (DAC), which optimises ...
An event-driven analogue-to-digital converter (ADC) architecture is proposed. The proposed architect...
This paper studies the impact of segmentation on current-steering digital-to-analog converters (DACs...
“This material is presented to ensure timely dissemination of scholarly and technical work. Copyrigh...
A compact current-mode Digital-to-Analog converter (DAC) suitable for biomedical application is repe...
In this thesis, we have explained the different types of DAC (Digital-to-Analog) architectures and t...
Presented is a 'Redundant Signed Digit' driving scheme for binary weighted D/A conversion. This sche...
It is well known that the performance of current steering D/A converters (DACs) is affected by paras...
It is well known that Nyquist DACs suffer from static as well as dynamic errors. In this paper, clas...
Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer...
Abstract—A digital random return-to-zero technique is pre-sented to improve the dynamic performance ...
This thesis describes theoretical and simulation-based work on digital-to-analog conversion ...
In this paper we present a new digital analog converter (DAC) design, based on the binary weighted r...
A 5-bit 2GS/s current-steering D/A converter for ultra-wideband (UWB) transceivers is presented in t...
A 9 bit 11 GS/s DAC is presented that achieves an SFDR of more than 50 dB across Nyquist and IM3 bel...
This paper presents a six-bit current-steering digital-to-analogue converter (DAC), which optimises ...
An event-driven analogue-to-digital converter (ADC) architecture is proposed. The proposed architect...
This paper studies the impact of segmentation on current-steering digital-to-analog converters (DACs...
“This material is presented to ensure timely dissemination of scholarly and technical work. Copyrigh...
A compact current-mode Digital-to-Analog converter (DAC) suitable for biomedical application is repe...
In this thesis, we have explained the different types of DAC (Digital-to-Analog) architectures and t...