How to efficiently implement dynamic circuit specialization systems

Dynamic Circuit Specialization (DCS) is a technique used to implement FPGA applications where some of the input data, called the parameters, change slowly compared to other inputs. Each time the parameter values change, the FPGA is reconfigured by a configuration that is specialized for those new parameter values. This specialized configuration is much smaller and faster than a regular configuration. However, the overhead associated to the specialization process should be minimized to achieve the desired benefits of using the DCS technique. This overhead is represented by both the FPGA resources needed to specialize the FPGA at run-time and by the specialization time. The introduction of Parameterized Configurations~\cite{bruneel2008agorpc} has improved the efficiency of the DCS implementations. However, the specialization overhead still takes a considerable amount of resources and time. In this paper, we explore how to efficiently build DCS systems by presenting a variety of possible solutions for the specialization process and the overhead associated to each of them. We split the specialization process into two main phases: the evaluation and the configuration phase. The PowerPC embedded processor, the MicroBlaze and a Customized Processor (CP) are used as alternatives in the evaluation phase. In the configuration phase, the ICAP and a custom configuration interface (SRL configuration) are used as alternatives. Each solution is used to implement a DCS system for three applications: an adaptive Finite Impulse Response (FIR) filter, a Ternary Content-addressable Memory (TCAM) and a Regular Expression matcher (RegEx). The experiments show that the use of our CP along with the SRL configuration achieves the minimum overhead in terms of the resources and the time. Our CP is 1.8 and 3.5 times smaller than the PowerPC and the area optimized implementation of the MicroBlaze respectively. Moreover, the use of the CP enables a more compact representation for the Parameterized Configuration in comparison to both the PowerPC and the MicroBlaze processors. For instance, in the FIR, the Parameterized Configuration compiled for our CP is 6-7 times smaller than that for the embedded processors