3D stacking of ultrathin chip packages: an innovative packaging and interconnection technology

In order to increase the functionality of electronic devices, while reducing the overall size and weight of the electronic chip packages, electronic chip packages can be combined into a 3D assembly. In this field we present a technology for stacking of multiple chip packages, resulting in a total volume almost equal to that of a single bare die. The technology is based on batch-processed ultra-thin chip packages (UTCPs) with a fine pitch metal fan-out. Package-on-package (PoP) technology enables stacking of UTCPs by vacuum lamination, followed by through hole interconnection technology for making contacts to the metal fan-out of the embedded UTCPs within the stack. The individual chip packages can be tested before stacking