Automatically mapping applications to a self-reconfiguring platform

The inherent reconfigurability of SRAM-based FPGAs enables the use of configurations optimized for the problem at hand. Optimized configurations are smaller and faster than their generic counterparts and therefore use the FPGAs resources more efficiently. However, when the problem at hand changes, two overheads are introduced: generating the new configuration and reconfiguring the FPGA. Many authors have tried to reduce these overheads with various success. The most successful implementations are hand designs for one specific application. The methods used in these implementations are hard to port to other applications, which results in a big design cost. To make runtime reconfiguration feasible in commercial designs, automated design methods are needed. In this paper, we describe a tool flow that automatically maps an application to a self-reconfiguring platform. This platform contains a configuration manager, responsible for the reconfiguration and an FPGA. In our case the Power PC (PPC) of a Xilinx FPGA is used as configuration manager. It uses the FPGA�s ICAP to reconfigure the FPGA. The tool flow is build around a reconfigurability-aware technology mapper called TMAP [2]. TMAP is an extension of a conventional technology mapper that produces a Tunable LUT circuit, i.e., a LUT circuit in which some of the LUT truth tables are expressed as functions of a set of parameters. The input of the tool low is an annotated HDL design, that describes the functionality that needs to be implemented. The flow outputs an FPGA configuration and a set of C functions. The FPGA configuration is used to configure the FPGA at startup and the C-functions are used by the PPC to adapt this configuration at run-time. The approach is successfully used to automatically implement an adaptive filter on the Xilinx XUP board