Synchronous delay based UWB pulse generator in FPGA

This paper presents an architecture for generating UWB pulses with a high centre frequency accuracy. The architecture allows to generate frequencies twice that of the FPGA clock using synchronous delays and is implementable in all types of FPGA. With a FPGA clock of 150 MHz, we generate RF pulse of 300 MHz with a maximum fractional bandwidth of 30%. The architecture also allows pulse width increment in steps of the clock period