Performance Analysis of Full Adder using Ganged CMOS Threshold Element with Different Technologies

A threshold gate is a type of digital logic gate that has multiple inputs and a single output. The output of the gate is determined by the number of inputs that are at a high (or 1) state. The threshold value, or number of inputs required to be at a high state, is set by the design of the gate. These gates are used in digital circuits to perform Boolean logic operations and are commonly used in computer processors and other digital devices. The inputs are multiplied by weights (Wi) and added to produce a resultant sum, which is then compared with threshold value ‘T’ to get the output Y. The values of weights and threshold should be real, finite, positive or negative numbers. In this paper we have designed a Ganged Complementary Metal Oxide Semiconductor Field Effect Transistor (GCMOS) 1- bit Full-Adder (FA) circuit. For all the simulations, A, B and Cin are taken as three binary inputs. The major advantage of this Ganged CMOS logic based FA circuit is its simplicity and lower transistor count. The circuit is simulated using Microwind tool with 50nm, 70nm and 90nm CMOS technologies