FPGA Based Implementation of a Multiplier-less FIR Filter for ECG Signal Processing

This research work presents an efficient digital system using Field Programmable Gate Array (FPGA) to filter the Electrocardiogram (ECG) signal. Finite Impulse Response (FIR) Digital filter is being used to preprocessing and denoising the ECG signal. The Reduce Adder Graph (RAG) algorithm has been incorporated in implementation of the FIR filter which reduces not only the size and cost but also decreases the computational time significantly. This work has achieved the target of 50Hz noise cancellation. The output of ECG signal is then compared with the ECG signal before and after filtering by plotting the signal both in time and frequency domain using MATLAB tools. The entire system has been implemented on the ALTERA DE-II FPGA education board by synthesizing Verilog HDL using Quartus II tool