An FPGA implementation of systolic array for Montgomery multiplication

Public-key cryptographic algorithms such as RSA algorithm require modular multiplications of very large operands. In RSA, the higher security the larger operand size which may reduce the clock rate and result to lower throughput This paper presents a fully systolic linear-array for the computation of Montgomery modular multiplication that is implemented using FPGA. Our fully systolic design shows that a high and nearly constant clock rate is achievable regardless of the size of the operand. As co1npared with the non-fully systolic architecture, our design offers higher frequency that yields a higher throughput rate and a lower area-time product. The total execution time for an 11- bit modular multiplication is 3n+1 cycles, latency of 2n+1, where n is the length of the modulus and a throughput of 1 bit per clock cycle