Calibrage mixte du décalage de l'horloge dans les convertisseurs analogique numérique à entrelacement temporel

Clock-skew errors in time-interleaved ADCs importantly degrade the linearity of such converters. These nearly constant but unknown errors, that must not be confused with random jitter, prevent time-interleaved ADCs from performing uniform sampling. There are some different techniques of facing clock-skew errors : two-ranks sample-and-hold, channel randomization, global passive sampling, clock-edge reassignment, all-digital calibration techniques and all-analog calibration techniques. We propose a new kind of mixed-signal clock-skew calibration technique. Compared to the all-digital ones, ours distinguishes itself by the simplicity of its hardware elements. On the other hand, compared to the all-analog ones, ours keeps the inherent robustness of a digital clock-skew detection. A demonstrator shows the feasibility of our technique. This demonstrator consists of two 10-bit commercial ADCs, an FPGA to implement a digital clock-skew detector and an ASIC in a CMOS 0.35 µm technology to implement a digitally trimmable multi-phase sampling clock generator. In this highly hostile environment of interconnected discrete components, our demonstrator can correct an initial clock-skew of thousands of picoseconds with a granularity of 1.8 picoseconds