This letter presents a fully integrated on-chip digital mismatch compensation system for time-based time-interleaved (TI) data converters. The proposed digital compensation features blind calibration of gain, offset, and timing mismatches. The implemented system uses time-based sampling clock mismatch detection, achieving convergence within 32K samples, which is on par with analog-assisted background methods. A specialized filter structure compensates for timing mismatches of magnitude up to 0.21 of the sampling period, nearly triple the range of other published digital compensation methods, and is effective for input signals up to 0.92 Nyquist bandwidth. The on-chip digital correction achieves suppression of all mismatch tones to levels be...
Mismatches between the channels of timeinterleaved analog to digital converters (TI-ADCs) cause offs...
A low complexity all-digital background calibration technique based on statistics is proposed. The b...
This paper presents an all-digital background calibration technique for the time skew mismatch in ti...
This letter presents a fully integrated on-chip digital mismatch compensation system for time-based ...
The concept of a Time-Interleaved analog-to-digital converter (TI ADC) which comprises sub-ADCs (ch...
Time-interleaved analog-to-digital converters (TIADC) require channel matching in terms of offset, g...
We propose an algorithm for the digital background calibration of time-interleaved analog-to-digital...
This paper presents a fully digital background calibration technique of the gain and timing mismatch...
International audienceTime Interleaved ADCs (TIADCs) are a good solu-tion to implement high sampling...
National audience<p>Abstract—Sample-time mismatches between the channels of Time-Interleaved Analog-...
Analog-to-digital-conversion enables utilization of digital signal processing (DSP) in many applicat...
This paper presents a method for the on-chip measurement and correction of gain errors, offsets and ...
A technique for the digital background calibration of subsampling time-interleaved analog-to-digital...
The project displays an all-digital background calibration for timing mismatch in time-interleaved a...
Mismatches between the channels of timeinterleaved analog to digital converters (TI-ADCs) cause offs...
A low complexity all-digital background calibration technique based on statistics is proposed. The b...
This paper presents an all-digital background calibration technique for the time skew mismatch in ti...
This letter presents a fully integrated on-chip digital mismatch compensation system for time-based ...
The concept of a Time-Interleaved analog-to-digital converter (TI ADC) which comprises sub-ADCs (ch...
Time-interleaved analog-to-digital converters (TIADC) require channel matching in terms of offset, g...
We propose an algorithm for the digital background calibration of time-interleaved analog-to-digital...
This paper presents a fully digital background calibration technique of the gain and timing mismatch...
International audienceTime Interleaved ADCs (TIADCs) are a good solu-tion to implement high sampling...
National audience<p>Abstract—Sample-time mismatches between the channels of Time-Interleaved Analog-...
Analog-to-digital-conversion enables utilization of digital signal processing (DSP) in many applicat...
This paper presents a method for the on-chip measurement and correction of gain errors, offsets and ...
A technique for the digital background calibration of subsampling time-interleaved analog-to-digital...
The project displays an all-digital background calibration for timing mismatch in time-interleaved a...
Mismatches between the channels of timeinterleaved analog to digital converters (TI-ADCs) cause offs...
A low complexity all-digital background calibration technique based on statistics is proposed. The b...
This paper presents an all-digital background calibration technique for the time skew mismatch in ti...