Scalable and CMOS-compatible catalyst assisted chemical etch

The ability to reliably and repeatably control the geometry of high aspect ratio silicon nanostructures over large areas is essential for a variety of applications in electronics, energy, point-of-use healthcare and sensing. For about five decades, Moore’s Law consistently delivered computing devices with improved performance, lower power consumption and enhanced functionality, transitioning from 2D scaling to 3D device geometries. However, this transition to 3D has led to unique challenges in deep etching of nanoscale geometries by plasma etch, which limits creation of small and deep features. Metal Assisted Chemical Etching (MACE or MacEtch), an electroless catalyst-based wet etch discovered in 2000, has superior etch anisotropy and sidewall profile and can improve fabrication of high aspect ratio nanostructures. However, MACE literature has not demonstrated wafer-scale etch uniformity, lacks compatibility with CMOS fabrication due to the use of Au as a catalyst, and has limited exploration of complex geometries. Solving these challenges enables a MACE process that can be deployed broadly for a wide variety of CMOS and non-CMOS devices that require precise, high throughput, high yield nanofabrication. This thesis has demonstrated scalable solutions to address MACE challenges, with a focus on adoption in high volume nanomanufacturing. To that end, first, wafer-scale reliable and repeatable fabrication of high aspect ratio silicon nanostructures is presented, based on integrating nanoimprint lithography, metal assisted chemical etching, and spectroscopic scatterometry. Next, a precise experimental technique to study the onset of Si-NW collapse is discussed. This approach resulted in unprecedented ultrahigh aspect ratio Si-NWs for oversized wires separated by sub-50nm gaps. A new nanostructure collapse avoidance methodology was developed using these results. Further, with respect to CMOS-compatibility of the MACE process, a replacement for gold was explored. For the first time, a Ruthenium MACE process that is comparable in quality to Au MACE is reported here. This result is significant because Ruthenium is not only CMOS-compatible but has also already been introduced in the semiconductor fab as an interconnect material. Finally, this research has explored complicated geometries that are specific to CMOS devices such as FinFETs and DRAM cells, and provided MACE-based process flow details to further demonstrate the potential of this technology for next-generation nanodevices. The results in this thesis thus remove a significant barrier to adoption of MACE for scalable fabrication of ultrahigh aspect ratio semiconductor nanostructures, and provide new directions of research for creation of 3D semiconductor nanodevicesMechanical Engineerin