Low Power and Low Phase Noise VCO for PLL Application

In modern communication systems, the voltage-controlled oscillator is an important circuitry that has applications such as clock generations, wireless communication, synchronization, and frequency synthesis. The most concentration in VCO research has been lower phase noise, higher frequency, low power consumption, and wide tuning range. Each of the goals is reachable on its own at the cost of other goals in VCO design. There are tradeoffs in the design where in this thesis, the middle ground is found in order to achieve low phase noise and low power consumption. This paper will provide a detailed analysis of Low Phase Noise and Low power consumption VCO using 65nm technology. The design of the PLL is analyzed where the VCO effect is explained. The types of noise in the VCO that lower the phase noise are discussed in section 2.2.3. The circuit simulation will be demonstrated in order to achieve the goal of low phase noise and power consumption. Isolation techniques will be provided in order to make sure VCO operates properly. This paper will include full layout techniques used to make the VCO for the SSPLL application. Fabricated stand-alone VCO will be measured and compared to the simulation