Phase change memory (PCM) device associated with Ovonic Threshold Switch (OTS) selector is a proven solution to fill the gap between DRAM and mass storage. This technology also has the potential to be embedded in a high-end microcontroller. However, programming and reading phases efficiency is directly linked to the selector's leakage current and the sneak-path management. To tackle this challenge, we propose in this paper, a new sense amplifier able to generate an auto-reference taking into account leakage current of unselected cells, including a regulation loop to compensate voltage drop due to reading current sensing. This auto-referenced sense, built on the chargesharing principle, is designed on a 28nm FDSOI technology and validated th...
Sense amplifiers are important circuit components of a dynamic random access memory (DRAM), which fo...
We proposed a novel self-reference sense amplifier scheme for spin-transfer-torque magneto-resistanc...
This brief presents a system architecture designed to enable 1-bit-per-cell storage in Ge-rich phase...
Phase change memory (PCM) device associated with Ovonic Threshold Switch (OTS) selector is a proven ...
2021 IFIP/IEEE 29th International Conference on Very Large Scale Integration (VLSI-SoC), Singapour, ...
Abstract- A memory sense-amplifier self-calibrates during sense-line precharge to reduce the require...
While technology scaling enables increased density for memory cells, the intrinsic high leakage powe...
This paper presents a low-offset read sensing scheme for resistive memories. Due to increasing devic...
[[abstract]]A conventional latch-type sense amplifier in a static random access memory (SRAM) could ...
Static Random Access Memory (SRAM) have been used extensively in the market especially in product su...
Abstract—A sensing technique using a voltage-mode architec-ture, noise-shaping modulator, and digita...
Using a current-sensing scheme and novel circuit techniques, the amplifier achieves sensing speeds e...
With the rapid increase of leakage currents, non-volatile memories have become competitive candidate...
Using a current-sensing scheme and novel circuit techniques, the amplifier achieves sensing speeds e...
A sensing technique using a voltage-mode architecture, noise-shaping modulator, and digital filter (...
Sense amplifiers are important circuit components of a dynamic random access memory (DRAM), which fo...
We proposed a novel self-reference sense amplifier scheme for spin-transfer-torque magneto-resistanc...
This brief presents a system architecture designed to enable 1-bit-per-cell storage in Ge-rich phase...
Phase change memory (PCM) device associated with Ovonic Threshold Switch (OTS) selector is a proven ...
2021 IFIP/IEEE 29th International Conference on Very Large Scale Integration (VLSI-SoC), Singapour, ...
Abstract- A memory sense-amplifier self-calibrates during sense-line precharge to reduce the require...
While technology scaling enables increased density for memory cells, the intrinsic high leakage powe...
This paper presents a low-offset read sensing scheme for resistive memories. Due to increasing devic...
[[abstract]]A conventional latch-type sense amplifier in a static random access memory (SRAM) could ...
Static Random Access Memory (SRAM) have been used extensively in the market especially in product su...
Abstract—A sensing technique using a voltage-mode architec-ture, noise-shaping modulator, and digita...
Using a current-sensing scheme and novel circuit techniques, the amplifier achieves sensing speeds e...
With the rapid increase of leakage currents, non-volatile memories have become competitive candidate...
Using a current-sensing scheme and novel circuit techniques, the amplifier achieves sensing speeds e...
A sensing technique using a voltage-mode architecture, noise-shaping modulator, and digital filter (...
Sense amplifiers are important circuit components of a dynamic random access memory (DRAM), which fo...
We proposed a novel self-reference sense amplifier scheme for spin-transfer-torque magneto-resistanc...
This brief presents a system architecture designed to enable 1-bit-per-cell storage in Ge-rich phase...